Scaling trends of power noise in 3-D ICs

• Paper shows how power noise changes in 3-D ICs with CMOS and TSV technology scaling.
• Uniform distribution of P/G TSVs array exhibit lower on-chip power noise.
• An accurate and fast closed-form expression to calculate TSV equivalent inductance.
• Tradeoffs among TSV parameters, technologies, and power noise are discussed.

Power supply noise in three-dimensional integrated circuits (3-D ICs) considering scaled CMOS and through silicon via (TSV) technologies is the focus of this paper. A TSV and inductance aware cell-based 3-D power network model is proposed and evaluated. Constant TSV aspect ratio and constant TSV area penalty scaling, as two scenarios of TSV technology scaling, are discussed. A comparison of power noise among via-first, via-middle, and via-last TSV technologies with CMOS scaling is also presented. When the TSV technology is a primary bottleneck in high performance 3-D ICs, an increasing TSV area penalty should be adopted to produce lower power noise. As a promising TSV technology, via-middle TSVs are shown to produce the lowest power noise with CMOS technology scaling.