A formal framework for interfacing mixed-timing systems

System-on-chip designs are composed of modules working at different clock frequencies. These modules will communicate using control and data events. However, they cannot be directly connected as their events will not be synchronised. In this paper, we give a formal framework for a latency insensitive interconnect which can be used for assembling such modules.The interface guarantees that the events are sent in correct order and there is no loss of information. Also, any change in the latency of event transmission by the sender or un-availability of the receiver to receive an event is handled correctly. We prove properties of the interface using the tagged-signal framework and illustrate the construction of a mixed-timing system.

► We give a formal framework to connect modules working at different clock frequencies.
► We have extended the concept of latency insensitive systems to multiple clocks.
► We define a multiple clock interconnect buffer and prove that it is latency insensitive.
► This buffer can handle delays and has no loss of information.
► We show how to compose various modules to form a latency insensitive system.