Post-silicon debugging of PMU integration errors using behavioral models

Power Management Units (PMUs) are large integrated mixed-signal circuits, having several linear and switching regulators for supplying customized voltages to the components of a low power platform. The presence of analog components in the integration circuitry makes it very hard to eliminate all pre-silicon integration errors, including some common types of errors. During post-silicon debug the designer typically wants to rule out the common types of errors before considering other types of bugs. This is facilitated by a mechanism for mapping back from observed anomalies to these known types of integration errors. We present an approach that enables this task by creating a fault map through pre-silicon analysis of the PMU. The proposed pre-silicon analysis makes use of formal properties and behavioral models to accelerate simulation, and is thereby able to create the fault map within feasible limits of time. We present experimental results on industrial strength PMUs to demonstrate the feasibility of this step. We also present a post-silicon debugging approach, which uses the inverse of the fault map to shortlist the set of known types of integration errors that must be ruled out before looking for other forms of bugs.

► We study post-silicon debugging of errors in integrated power management circuits.
► Behavioral models are used to map integration errors to output anomalies.
► The map is created during pre-silicon validation and used during post-silicon debugging.
► We leverage our Chassis tool for automatic creation of behavioral models.
► Results on industrial test cases demonstrate the scalability and industrial relevance.