کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
538469 871093 2013 10 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
Timing–driven variation–aware synthesis of hybrid mesh/tree clock distribution networks
چکیده انگلیسی

Clock skew variations adversely affect timing margins, limiting performance, reducing yield, and may also lead to functional faults. Non-tree clock distribution networks, such as meshes and crosslinks, are employed to reduce skew and also to mitigate skew variations. These networks, however, increase the dissipated power while consuming significant metal resources. Several methods have been proposed to trade off power and wires to reduce skew. In this paper, an efficient algorithm is presented to reduce clock skew variations while minimizing power dissipation and metal area overhead. With a combination of nonuniform meshes and unbuffered trees (UBT), a variation-tolerant hybrid clock distribution network is produced. Clock skew variations are selectively reduced based on circuit timing information generated by static timing analysis (STA). The skew variation reduction procedure is prioritized for critical timing paths, since these paths are more sensitive to skew variations. A framework for skew variation management is proposed. The algorithm has been implemented in a standard 65 nm cell library using standard EDA tools, and tested on several benchmark circuits. As compared to other nonuniform mesh construction methods that do not support managed skew tolerance, experimental results exhibit a 41% average reduction in metal area and a 43% average reduction in power dissipation. As compared to other methods that employ skew tolerance management techniques but do not use a hybrid clock topology, an 8% average reduction in metal area and a 9% average reduction in power dissipation are achieved.


► A framework for skew variations management by prioritizing critical timing paths.
► Selectively reduction of clock skew variation based on circuit timing information.
► Variation-tolerant hybrid clock combining nonuniform meshes and unbuffered trees.
► Reducing skew variations while minimizing power dissipation and metal area overhead.
► Exhibits a 41% average reduction in metal area and a 43% average reduction in power.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 46, Issue 4, September 2013, Pages 382–391
نویسندگان
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