A new clock network synthesizer for modern VLSI designs

In nanometer-scale VLSI physical design, clock tree becomes a major concern on determining the total performance of the chip. Both the clock skew and the PVT (process, voltage and temperature) variations contribute a lot to the behavior of the digital circuits. Previous works mainly focused on skew and wirelength minimization. However, it may lead to negative influence on the variation factors. In this paper, a novel clock tree synthesizer is proposed for performance improvement. Several algorithms are introduced to tackle the issues accordingly. A dual-MST geometric approach of perfect matching is developed for symmetric clock tree construction. In addition, a special technique of buffer sizing is also introduced. These two techniques can help balancing the tree structure in order to reduce the variation effect. An iterative buffer insertion technique and the dual-MZ blockage handling technique are also presented. They are developed for proper distribution of buffers and connection of wires, so the dynamic power consumption can be reduced. Additionally, slew table construction and internal nodes relocation are involved to satisfy the slew rate constraint and further reduce the clock skew. Experimental results show that the performance of our synthesizer is better than those of the previous works.

► A dual-MST perfect matching algorithm is developed for symmetric clock tree construction.
► A look-up table based buffer sizing approach is developed for variation tolerance improvement.
► An iterative buffer insertion technique is developed for delay balancing and capacitance reduction.
► A dual-MZ blockage handling technique is developed for buffer location distribution and blockage avoidance.
► SPICE simulation is also applied for accurate delay estimation; the internal nodes of the clock tree can be relocated for further skew minimization.