کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
538585 | 871104 | 2011 | 13 صفحه PDF | دانلود رایگان |
To date, the best algorithms for performing placement on Field-Programmable Gate Arrays (FPGAs) are based on Simulated Annealing (SA). Unfortunately, these algorithms are not scalable due to the long convergence time of the latter. With an aim towards developing a scalable FPGA placer we present an analytic placement method based on a near-linear net model, called star+. The star+ model is a variant of the well-known star model and is continuously differentiable – a requirement of analytic methods that rely on the existence of first- and second-order derivatives. Most importantly, with the star+ model incremental changes in cost resulting from block movement can be computed in O(1) time, regardless of the size of the net. This makes it possible to construct time-efficient solution methods based on conjugate gradient and successive over-relaxation for solving the resulting non-linear equation system. When compared to VPR, the current state-of-the-art placer based on SA, our analytic method is able to obtain an 8–9% reduction in critical-path delay while achieving a speedup of nearly 5x when VPR is run in its fast mode.
Journal: Integration, the VLSI Journal - Volume 44, Issue 3, June 2011, Pages 192–204