Design of MOS transconductors with low noise and low harmonic distortion for minimum current consumption

This paper describes a method for analysis and design of MOS voltage-to-current converters (V–I converters or transconductors) and introduces a novel V–I converter circuit with significantly improved linearity performance. The proposed method uses harmonic compensation for the linearization of the V–I characteristics and introduces a normalized representation of the converter equations. The analysis is applied for several circuit topologies based on MOS differential pairs. The circuits are compared with respect to their current consumption, signal to noise ratio, achievable linearity and bandwidth. The minimum required current consumption for certain linearity and dynamic range is derived. The proposed novel V–I converter circuit uses a combination of local resistive feedback and cross-coupling. In this way, it achieves significant, simultaneous suppression of the third and the fifth order harmonic components in the transconductor output current. The implementation constraints and the performance of the new circuit solution are evaluated via simulations on transistor level. A standard digital 0.18 micrometer, 1.8 V, CMOS process is used.