Frame buffer-less stream processor for accurate real-time interest point detection

• Processor for identification and refinement of IPs in images for VS applications.
• Streaming elaboration on data received from image sensors.
• On-chip SRAM or DPREG in place of frame buffers and off-chip memory.
• Accuracy comparable with the software pipe of the MPEG standardization process.
• Implementation oriented to Field-Programmable Logics (FPL) and ASIC std_cells.

A high performance HW accelerator is proposed to extract and refine the Interest Points from images, by accurately calculating the Difference-of-Gaussian and using refinement algorithms from the SIFT method. Unique features of the accelerator consist in an accuracy comparable to the CDVS Test Model, reference software; in the capability to process the incoming pixel in streaming order to minimize the amount of embedded memory and avoid external frame buffers; in the possibility to configure the processor with different area/speed ratios. FPGA synthesis on a Xilinx XC7V2000T returns a maximum operation frequency up of 309 MHz at the fastest corner. Standard cell synthesis with the STMICROELECTRONICS FDSOI 28 nm technology, de-congestioned by the use of DPREG memories in place of SRAM, gives a maximum frequency of 1.2 GHz and a power dissipation of about 1 W at the typical conditions.