کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
539638 1450237 2015 12 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Length-constrained escape routing of differential pairs
ترجمه فارسی عنوان
مسیریابی فرکانس محدود برای عبور از جفت های دیفرانسیل
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
چکیده انگلیسی


• Given a set of DPs, a length-constrained escape routing problem in DPs is formulated.
• All the DPs can be designed to satisfy the length constraint and avoid routing an acute angle.
• A two-phase escape routing algorithm is proposed for all local and global DPs.
• Our proposed approach obtains length-constrained escape routing results for tested examples.

In this paper, given a set of differential pairs (DPs) inside a single chip and the maximum tolerant length difference in a DP, a length-constrained escape routing problem in DPs is formulated. Firstly, the feasible merging connections and the feasible merging grids of all the DPs can be selected to satisfy the given length constraint and avoid routing an acute angle on a wire. Furthermore, based on the observation of the DP escape routing results from industrial boards, all the DPs can be divided into global and local DPs. By using two-phase escape routing, some local DPs can be escaped under the direction constraint and routed by using direct paths in direct escape routing and the unrouted local DPs and the global DPs can be escaped and routed by using obstacle-aware shortest paths in iterative obstacle-aware flow-based escape routing. Compared with Yan׳s escape router [11] and Li׳s escape router [12], the experimental results show that our proposed approach uses a shorter total wirelength under the larger length constraint and reduces 79.6% and 46.8% of the CPU time on the average to achieve 100% escape routability for six tested examples, respectively. Additionally, our proposed approach can obtain length-constrained escape routing results with the avoidance of routing an acute angle under the smaller length constraint for the tested example in the reasonable CPU time.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 48, January 2015, Pages 158–169
نویسندگان
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