Full-Swing Gate Diffusion Input logic—Case-study of low-power CLA adder design

• We propose an improved methodology (FS-GDI) for designing low power and low area digital circuits. The proposed methodology is applied to a standard design of Carry Look Ahead Adder (CLA), which is implemented in 40 nm technology node.
• We prove (through statistical Monte Carlo simulations) that the proposed FS-GDI CLA presents full functionality and robustness under global and local process variations.
• We discuss leakage reduction in GDI through minimum leakage vector (MLV) analysis.
• We show low voltage operation of the GDI cells, including minimum energy operation (MEP).
• We show that the designed CLA presents 2× area reduction, 5× improvement in dynamic energy dissipation and 4× decrease in leakage, when compared to the CMOS CLA.

Full Swing Gate Diffusion Input (FS-GDI) methodology is presented. The proposed methodology is applied to a 40 nm Carry Look Ahead Adder (CLA). The CLA is implemented mainly using GDI full-swing F1 and F2 gates, which are the counterparts of standard CMOS NAND and NOR gates. A 16-bit GDI CLA was designed in a 40 nm low power TSMC process. The CLA, implemented according to the proposed methodology, presents full functionality and robustness under global and local process variations at wide range of supply voltages. Simulation results show 2× area reduction, 5× improvement in dynamic energy dissipation and 4× decrease in leakage, with a slight (24%) degradation in performance, when compared to the CMOS CLA. Advanced design metrics of GDI cells, such as minimum energy point (MEP) operation and minimum leakage vector (MLV), are discussed.