Regularity-constrained floorplanning for multi-core processors

Regularity-Constrained Floorplanning for Multi-Core Processors.
• Floorplanning with constraints on partial regularity blocks for multi-processors.
• Proposed a new algorithm to achieve the global optimization on target.
• The algorithm can also reduce floorplanning time with great efficiency and area usage.
• This research can be applied to both digital and analog circuits

Multi-core technology becomes a new engine that drives performance growth for both microprocessors and embedded computing. This trend requires chip floorplanners to consider regularity constraint since identical processing/memory cores are preferred to form an array in layout. In general, regularity facilitates modularity and therefore makes chip design planning easier. As chip core count keeps growing, pure manual floorplanning will be inefficient on the solution space exploration while conventional floorplanning algorithms do not address the regularity constraint for multi-core processors. In this work, we investigate how to enforce regularity constraint in a simulated annealing based floorplanner. We propose a simple and effective technique for encoding the regularity constraint in sequence-pairs. To the best of our knowledge, this is the first work on regularity-constrained floorplanning in the context of multi-core processor designs. Experimental comparisons with a semi-automatic method show that our approach yields an average of 12% less wirelength and mostly smaller area.