Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs

• A new FPGA architecture is proposed that consists of asynchronous data transmission devices.
• An algorithm is presented to select suitable wire segments to use data serializing resources.
• Routing resource usage is improved by 18.81% on average.
• Routing congestion is reduced by 48.73% on average.
• No performance degradation and slight power and area overhead.

Asynchronous serial transceivers have been recently used for data serializing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the asynchronous serial transmission but they have serious challenges to use this technology. In this paper, we present a new FPGA architecture corresponding with a new routing algorithm to use the asynchronous data serializing technique in modern FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (18.81% and 48.73%, respectively) by using the asynchronous data serializing without any performance degradation in cost of reasonable overhead in area and power consumption. The resulting improvements will increase for larger and more complex FPGAs.