Efficient modulo 2n+1 multiply and multiply-add units based on modified Booth encoding

• Modulo 2n+1 modified Booth multiplication algorithm for operands in weighted representation.
• Fused modulo 2n+1 multiply-add units based on the same algorithm are also described.
• Circuit area savings of average 15% preserving the maximum speed achievable.
• Power improvements of average 10% for the multiplier and 21% for the multiply-add unit.
• Strong candidates for the arithmetic subsystem in fast DSP cores.

In this work a new efficient modulo 2n+1 modified Booth multiplication algorithm for both operands in the weighted representation is proposed. Furthermore, the same algorithm is extended to realize modulo 2n+1 multiply-add units. The derived partial products are reduced by an inverted end around carry-save adder tree to two operands, which are finally added by a modulo 2n+1 adder. The performance and efficiency of the proposed multipliers are evaluated and compared against the earlier modulo 2n+1 multipliers, based on a single gate level model. Comparisons based on experimental CMOS implementations for both the multiply and multiply-add units are also given. The proposed multipliers yield area and power savings by an average of 15% and 10% respectively, while the corresponding area and power savings of the proposed multiply-add units are 14% and 21% respectively.