کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
539700 871269 2014 12 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Dual-rail asynchronous logic multi-level implementation
ترجمه فارسی عنوان
پیاده سازی سطح چندگانه ناهمزمان دوگانه ای
کلمات کلیدی
منطق ناهمزمان، تجزیه، اجرای چند سطح، شبکه بولی، گره
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
چکیده انگلیسی

A synthesis flow oriented on producing the delay-insensitive dual-rail asynchronous logic is proposed. Within this flow, the existing synchronous logic synthesis tools are exploited to design technology independent single-rail synchronous Boolean network of complex (AND-OR) nodes. Next, the transformation into a dual-rail Boolean network is done. Each node is minimized under the formulated constraint to ensure hazard-free implementation. Then the technology dependent mapping procedure is applied. The MCNC and ISCAS benchmark sets are processed and the area overhead with respect to the synchronous implementation is evaluated. The implementations of the asynchronous logic obtained using the proposed (with AND-OR nodes) and the state-of-the-art (nodes are designed based on DIMS, direct logic and NCL) network structures are compared. A method, where nodes are designed as simple (NAND, NOR, etc.) gates is chosen for a detailed comparison. In our approach, the number of completion detection logic inputs is reduced significantly, since the number of nodes that should be supplied with the completion detection is less than in the case of the network structure that is based on simple gates. As a result, the improvement in sense of the total complexity and performance is obtained.


► A synthesis flow producing a boolean network of complex nodes is proposed.
► Each node is minimized under the constraint to ensure hazard-free implementation.
► The technology-dependent mapping procedure is proposed.
► The number of completion detection logic inputs is reduced significantly.
► The improvement in sense of the total complexity and performance is obtained.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 47, Issue 1, January 2014, Pages 148–159
نویسندگان
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