کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
539908 | 871277 | 2012 | 11 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
A framework for low power synthesis of interconnection networks-on-chip with multiple voltage islands
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
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چکیده انگلیسی
The problem of VI-aware Network-on-Chip (NoC) design is extremely challenging, especially with the increasing core counts in today's power-hungry Chip Multiprocessors (CMPs). In this paper, we propose a novel framework for automating the synthesis of regular NoCs with VIs, to satisfy application performance constraints while minimizing chip power dissipation. Our proposed framework uses a set of novel algorithms and heuristics to generate solutions that reduce network traffic by up to 62%, communication power by up to 32%, and total chip power dissipation by up to 13%, compared to the best known prior work that also solves the same problem.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 45, Issue 3, June 2012, Pages 271–281
Journal: Integration, the VLSI Journal - Volume 45, Issue 3, June 2012, Pages 271–281
نویسندگان
Nishit Kapadia, Sudeep Pasricha,