Generalized high speed Itoh–Tsujii multiplicative inversion architecture for FPGAs

Among all finite field operations, finite field inversion is the most computationally intensive operation. Yet, it is an essential component of several public-key cryptographic algorithms such as elliptic curve cryptography. For hardware implementations over extended binary fields, the Itoh–Tsujii inversion algorithm (ITA) is the most efficient. In this paper we propose acceleration techniques for ITA on FPGA platforms. We first propose a generalization of the parallel ITA which uses exponentiation by 2n and 2n, where n≥1n≥1. Parallel ITA has several drawbacks which limit its speed. We propose a novel technique supported with theoretical analysis to overcome the drawbacks. The technique reduces the critical delay of the ITA architecture without increasing the clock cycle requirement. Experimental results are presented to show that the proposed technique outperforms reported results.