کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
540134 871288 2009 11 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
A novel low-power full-adder cell for low voltage
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
A novel low-power full-adder cell for low voltage
چکیده انگلیسی

This paper presents a novel low-power majority function-based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure. It can work reliably at low supply voltage. In this design, the time-consuming XOR gates are eliminated. The circuits being studied are optimized for energy efficiency at 0.18-μm CMOS process technology. The adder cell is compared with seven widely used adders based on power consumption, speed, power-delay product (PDP) and area efficiency. Intensive simulation runs on a Cadence environment and HSPICE show that the new adder has more than 11% in power savings over a conventional 28-transistor CMOS adder. In addition, it consumes 30% less power than transmission function adder (TFA) and is 1.11 times faster.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 42, Issue 4, September 2009, Pages 457–467
نویسندگان
, , , , ,