کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
540197 | 871293 | 2009 | 9 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Two-phase synchronization with sub-cycle latency
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله

چکیده انگلیسی
Synchronizers typically incur long latency of multiple-clock cycles, resulting in low throughput. This paper presents two novel fast synchronizers, both based on two-phase protocols: a two-flip-flop synchronizer which reduces the data cycle from 6–12 down to 2–4 clock cycles, and a LDL synchronizer which strives for maximum throughput and ‘sub-cycle latency,’ namely data transfers that incur no extra penalty due to synchronization. These synchronizers are useful for data transfers over long interconnects. Simulations of best- and worst-case scenarios are presented which demonstrate the improved performance of the novel synchronizers. The results are compared to two-clock FIFO and to conventional two-flip-flop synchronizers.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 42, Issue 3, June 2009, Pages 367–375
Journal: Integration, the VLSI Journal - Volume 42, Issue 3, June 2009, Pages 367–375
نویسندگان
Rostislav (Reuven) Dobkin, Ran Ginosar,