کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
540294 871304 2008 17 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
On VLSI design of rank-order filtering using DCRAM architecture
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
On VLSI design of rank-order filtering using DCRAM architecture
چکیده انگلیسی

This paper addresses on VLSI design of rank-order filtering (ROF) with a maskable memory for real-time speech and image processing applications. Based on a generic bit-sliced ROF algorithm, the proposed design uses a special-defined memory, called the dual-cell random-access memory (DCRAM), to realize major operations of ROF: threshold decomposition and polarization. Using the memory-oriented architecture, the proposed ROF processor can benefit from high flexibility, low cost and high speed. The DCRAM can perform the bit-sliced read, partial write, and pipelined processing. The bit-sliced read and partial write are driven by maskable registers. With recursive execution of the bit-slicing read and partial write, the DCRAM can effectively realize ROF in terms of cost and speed. The proposed design has been implemented using TSMC 0.18μm 1P6M technology. As shown in the result of physical implementation, the core size is 356.1×427.7μm2 and the VLSI implementation of ROF can operate at 256 MHz for 1.8 V supply.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 41, Issue 2, February 2008, Pages 193–209
نویسندگان
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