Electromigration-aware analog Router with multilayer multiport terminal structures

• Innovative electromigration (EM)-aware methodology for automatic generation of analog IC layouts.
• EM-aware methodology embedded on an analog IC design automation environment.
• First dedicated EM-aware analog routing approach considering multiport multiterminal signal nets.
• Complete design flow demonstrated for the UMC 130 nm design process.
• Validated using the industrial grade Calibre® tool.

The combined effects of current densities and temperature in the interconnects may cause the failure of a circuit due to electromigration (EM). EM becomes increasingly more relevant with the ongoing reduction in circuit sizes caused by the evolution of nanoscale integration processes. Therefore EM effects must be taken into account in the design of both power networks and signal wires of analog or mixed-signal integrated circuits (ICs), to make their impact on the circuits’ reliability negligible. In previous EM-aware analog IC routing approaches, ‘dot-models’ are assumed for the terminals, i.e. each terminal has only one port that needs to be routed; however, in practice, analog standard cells usually contain multiple electrically-equivalent locations, often distributed over different fabrications layers, where legal connections can be made, multiport terminals, which need to be properly explored. This paper describes an EM-aware routing methodology considering multiport multiterminal signal nets of analog ICs. The complete design flow is detailed and demonstrated with experimental results and also, by generating the routing for two typical analog circuit structures for the UMC 130 nm design process; the automatically generated layouts are validated using the industrial grade Calibre® tool.