کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
541013 | 871370 | 2014 | 11 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs
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کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs A geometric approach to chip-scale TSV shield placement for the reduction of TSV coupling in 3D-ICs](/preview/png/541013.png)
چکیده انگلیسی
In 3D ICs, through-silicon-vias (TSVs) can suffer from cross coupling if signal integrity is not considered during the design process. In this paper, coupling between TSVs is modeled, and a chip-scale TSV shielding scheme is presented. A geometric model is developed to estimate TSV coupling. The low complexity of the geometric model makes it practical for chip-scale shield placement optimization. Two shield placement algorithms are presented and compared to standard shield placement techniques that use a high complexity circuit model of coupling. Results show that our algorithms are able to reduce the total cross coupling in a layout on average 111%/129% more than standard methods.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 47, Issue 3, June 2014, Pages 307–317
Journal: Integration, the VLSI Journal - Volume 47, Issue 3, June 2014, Pages 307–317
نویسندگان
Caleb Serafy, Bing Shi, Ankur Srivastava,