Bitmask aware compression of NISC control words

It is not always feasible to implement an application specific custom hardware due to cost and time considerations. No instruction set compiler (NISC) architecture is one of the promising directions to design a custom datapath for each application using its execution characteristics. A major challenge with NISC control words is that they tend to be at least 4–5 times larger than regular instruction size, thereby imposing higher memory requirement. A possible solution to counter this is to compress these control words to reduce the code size of the application. This paper proposes an efficient bitmask-based compression technique to drastically reduce the control word size while keeping the decompression overhead in an acceptable range. The main contributions of our approach are (i) smart encoding of constant and less frequently changing bits, (ii) efficient do not care resolution for maximum bitmask coverage using limited dictionary entries, (iii) run length encoding to significantly reduce repetitive control words and (iv) design of an efficient decompression engine to reduce the performance penalty. Our experimental results demonstrate that our approach improves compression efficiency by an average of 20% over the best known control word compression, giving a compression ratio of 25–35%. In addition, our technique only requires 1–3 on-chip RAMs, thus making it suitable for FPGA implementation.

► NISC designs custom datapath for each application using its execution characteristics.
► NISC control words 4–5 times more than regular instruction size.
► A bitmask-based compression algorithm is proposed for NISC control word compression.
► The proposed approach encodes constant and less frequently changing words efficiently.
► Effective do not care resolution for maximum bitmask coverage using limited dictionary entries is proposed.