Multi-bend bus-driven floorplanning considering fixed-outline constraints

The rapid rate of technological advances makes it necessary for very large scale integration (VLSI) floorplanning to consider not only interconnect constraints, but also fixed-outline constraints. In this paper, we propose a new approach to address the problem of Bus-Driven Floorplanning (BDF) within a fixed die. By providing the width and height of a chip, a set of circuit blocks and the bus specifications (i.e., the width of each bus and the blocks that the bus needs to go through), the approach will generate a final floorplan that satisfies the following requirements: (a) all blocks are packed within the fixed outline, (b) all buses are routable and (c) the floorplan area and total bus area are minimized. Based on the deterministic algorithm Less Flexibility First (LFF), our approach does not need to resort to a floorplan representation and functions very well in fixed-outline floorplanning. Our approach places no limitations on the shape of the buses, and the processes of block packing and bus packing proceed simultaneously. According to the experimental results, our approach can generate a good solution with a lower percentage of dead space, a shorter total length of all buses and a shorter run time, even under fixed-outline constraints. In addition, our algorithm works well for large and complex test cases that have not been studied in previous research.

► Our paper focuses on solving the bus driven floorplanning under fixed-outline constraints.
► A deterministic algorithm Less Flexibility First, which functions well in this problem, is adopted.
► In our algorithm, bus constraints can affect the block-packing process.
► Compared with previous works, our approach has better performance.
► For larger and more complex cases, which are not involved in previous works, our algorithm still functions well.