کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
541065 1450238 2007 12 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Wire shaping of RLC interconnects
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
Wire shaping of RLC interconnects
چکیده انگلیسی

The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown to exhibit a general exponential form. The line inductance makes exponential tapering more attractive for RLC lines than for RC lines. For RLC lines, optimum wire tapering achieves a greater reduction in the signal propagation delay as compared to uniform wire sizing. For RLC   lines, exponential tapering outperforms uniform repeater insertion. As technology advances, wire tapering becomes more effective than repeater insertion, since a greater reduction in the propagation delay is achieved. Optimum wire tapering achieves a reduction of 36%36% in the propagation delay in long RLC interconnect as compared to uniform repeater insertion.Wire tapering can reduce both the propagation delay and power dissipation. Optimum tapering for minimum propagation delay reduces the propagation delay by 15%15% and power dissipation by 16%16% for an example circuit. The optimum tapering factor to minimize the transient power dissipation of a circuit is described in this paper. An analytic solution to determine the optimum tapering factor that exhibits an error of less than 2% is provided. Wire tapering is also shown to reduce the power dissipation of a circuit by up to 65%.Wire tapering can also improve signal integrity by reducing the inductive noise of the interconnect lines. Wire tapering reduces the effect of impedance mismatch in digital circuits. The difference between the overshoots and undershoots in the signal waveform of an example clock distribution network is decreased by 34%34% as compared to a uniformly sized network producing the same signal characteristics.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Integration, the VLSI Journal - Volume 40, Issue 4, July 2007, Pages 461–472
نویسندگان
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