An efficient multiplier-less architecture for 2-D convolution with quadrant symmetric kernels

Design of a high-performance digital architecture for computing 2-D convolution utilizing the quadrant symmetry of the kernels is proposed in this paper. Pixels in the four quadrants of the kernel region with respect to an image pixel are considered simultaneously for computing the partial results of the convolution sum. The new architecture performs computations in the logarithmic domain by utilizing novel multiplier-less log2 and inverse-log2 modules. An effective data-handling strategy is developed in conjunction with the logarithmic modules to eliminate the necessity of multipliers in the architecture. The systolic architecture employs parallel and pipelined processing and is able to produce one output every clock cycle. The new design resulted in approximately 40% reduction in hardware resource when compared to the approach of multiplier-based quadrant symmetric architecture. The proposed architecture design is capable of performing convolution operations for 63.3, 1024×1024 frames or 66.4 million outputs per second with 22×22 kernel in a Xilinx's Virtex 2v2000ff896-4 FPGA at maximum clock frequency of 66.4 MHz. The error analysis performed in two image-processing applications of edge detection and noise filtering shows that the hardware implementation with proposed design provides accurate results similar to the software implementation.