An area-efficient timing closure technique for FPGAs using Shannon's expansion

This paper presents a technique to optimize the speed performance of circuits implemented in FPGAs. After synthesis, technology mapping and placement are complete, we apply Shannon's expansion to the most critical sections of the circuit. This approach allows us to precompute the values of functions that depend on late-arriving critical signals and use a multiplexer to quickly select the appropriate value when the signal arrives. Any new logic elements created by this technique are incrementally placed in a minimally disruptive fashion to ensure convergence between the circuit optimization and the netlist placement. Experimental results show that this technique can improve the performance of circuits by 11% on average, and up to 30% in some cases.