An 8 bit, 100 kS/s, switch-capacitor DAC SAR ADC for RFID applications

An 8 bit switch-capacitor DAC successive approximation analog to digital converter (SAR-ADC) for sensor-RFID application is presented in this paper. To achieve minimum chip area, maximum simplicity is imposed on capacitive DAC; replacing capacitor bank with only a one switch-capacitor circuit. The regulated dynamic current mirror (RDCM) design is introduced to provide stabilized current. This invariable current from RDCM, charging or discharging the only capacitor in circuit is controlled by pulse width modulated signal to realize switch capacitor DAC. The switch control scheme is built using basic AND gates to generate the control signals for RDCM. Only one capacitor and reduced transistor count in digital part reduces the silicon area occupied by the ADC to only 0.0098 mm2. The converter, designed in GPDK 90 nm CMOS, exhibits maximum sampling frequency of 100 kHz & consumes 6.75 µW at 1 V supply. Calculated signal to noise and distortion ratio (SNDR) at 1 V supply and 100 kS/s is 48.68 dB which relates to ENOB of 7.79 bits. The peak values of differential and integral nonlinearity are found to be +0.70/−0.89 LSB and +1.40/−0.10 LSB respectively. Evaluated figure of merit (FOM) is 3.87×1020, which show that the proposed ADC acquires minimal silicon area and has sufficiently low power consumption compared to its counterparts in RFID applications.