کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
541290 | 871456 | 2015 | 6 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
A ±3.07% frequency variation clock generator implemented using HV CMOS process
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله

چکیده انگلیسی
In this paper, we propose a clock generator with a feedback TPC (temperature and process compensation) bias circuit fabricated by a high-voltage (HV) CMOS process. Particularly, the feedback TPC bias is composed of an OPA, MOS transistors and resistors, where large BJT devices are no longer needed such that it is easy to be integrated on chip with small area overhead. The feedback TPC bias circuit, including a MOS transistor, four resistors, and a differential amplifier, is used to provide temperature and process compensation. The proposed circuit design is implemented using 0.25 μm 60 V BCD process. Measurement of 10 dies in the range of 0 °C to 100 °C is carried out to verify that the worst frequency drifting error is ±3.07%.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 46, Issue 4, April 2015, Pages 285–290
Journal: Microelectronics Journal - Volume 46, Issue 4, April 2015, Pages 285–290
نویسندگان
Chua-Chin Wang, Deng-Shian Wang, Tzu-Chiao Sung, Yi-Jie Hsieh, Tzung-Je Lee,