Process variability-induced NoC link failure: A probabilistic model

• This research models current and delay variations resulting from process variations across Networks-on-Chip (NoC) links.
• This paper also proposes a model for the statistical probability for link failure.
• We study the effect of supply and frequency scaling on link failure probability at different technology nodes.
• Results show that link failure probability reaches 3.7% for 4×4 meshes.
• It is shown that the link failure probability increases as the supply voltages decreases or the clock frequency increases.

As technology scales down, the amount of process variations increases causing Networks-on-Chip (NoC) links, designed to be identical, to have current and delay variations. Thus, some links may fail to meet design timing or power constraints. Using current and delay variations with design constraints, we estimate link failure probability across NoC links. Modeling results show that the average NoC link failure probability across a 4×4 mesh reaches 3.3% for voltage mode (VM) links and 3.7% for current mode (CM) links at 32 nm. The average NoC link failure probability also increases as the supply voltage decreases or the operating frequency increases. As NoC mesh size scales from 4×4 to 8×8, the link failure probability doubles to 8% for VM links at 22 nm. Topology evaluation shows that for small NoC size, the grid topology outperforms the tree one with lower amount of variation. On the other hand, for relatively large NoC sizes, the hierarchical tree and ring topologies outperform the grid topology with lower amount of variations across the links.

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