A low-jitter wide-range duty cycle corrector for high-speed high-precision ADC

This paper presents a duty cycle corrector (DCC) circuit for high-speed and high-precision pipelined A/D converter. Combined charge pump is used to ensure the stability of the current source and the current sink, and the charge sharing effect can be suppressed to improve the accuracy of the duty cycle of the output clock. The added second-order low-pass filter with Miller capacitance to the differential output of combined charge pump not only saves the area, but also improve the loop stability, which making wider range of input duty cycle (10–90%). The circuit can also effectively suppress the clock jitter. The post-simulation results are based on SMIC 65 nm CMOS process. The duty cycle accuracy of output clock signal in the proposed DCC is 50±0.2%. In 200 MHz input frequency, 27 °C TT process corner, RMS jitter is about 186.6 fs, Peak-to-Peak jitter is about 1.447 ps. With 2.5 V supply voltage, the power consumption is 1.88 mW and the active chip area is 0.02 mm2. This work has been successfully applied in 13-bit 200MSPS A/D converter.