A power-efficient reference buffer with wide swing for switched-capacitor ADC

highlights
• A level-shifter-aided reference buffer is proposed for high speed and high resolution switched-capacitor ADC.
• Output swing is increased by a level-shifter.
• Power consumption is saved by NMOS-only Buffer Branch.
• High PSRR is achieved by the proposed buffer.

A level-shifter-aided CMOS reference voltage buffer with wide swing for high-speed high-resolution switched-capacitor ADC is proposed. It adopts a level shifter for wide swing and a NMOS-only branch circuit for low power. High PSRR (power supply rejection ratio) is guaranteed by the proposed architecture. The proposed reference buffer is integrated in a 14-bit 150 MSps low-power pipelined ADC with the amplification phase of only 2.5 ns. With the input of 2.4 MHz and 2 Vp-p, the measurement of the fabricated ADC shows that the SNDR is 71.3 dB and the SFDR is 93.6 dBc. And the power consumption of the reference buffer is 17 mW from a 1.3 V power supply.