کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
541456 871471 2013 10 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
Drain current model for a gate all around (GAA) p–n–p–n tunnel FET
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
Drain current model for a gate all around (GAA) p–n–p–n tunnel FET
چکیده انگلیسی

A two dimensional drain current model has been proposed for a gate all around silicon p–n–p–n (pocket doped or tunnel source) tunnel field effect transistor (TFET) including the influence of drain voltage and source/drain depletion widths. The results extracted through numerical simulations have been used to obtain a semi empirical formulation of tunnel barrier width (LBW) which captures the dependence of gate voltage, drain voltage, and geometrical parameters (radii (R) and gate oxide thickness (tox)). The model is then used for evaluating various electrical parameters such as: drain current Ids, sub-threshold swing (SS), trans-conductance (gm), and device efficiency (gm/Ids). The impact of scaling R and tox on the above mentioned parameters have also been investigated. Moreover, the model depicts the influence of pocket doping and pocket width (which are crucial parameters for optimization of p–n–p–n TFET performance) on the energy band profile of a p–n–p–n TFET very well. The modeled results are in good agreement with the device simulation results.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 44, Issue 6, June 2013, Pages 479–488
نویسندگان
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