کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
541461 | 871471 | 2013 | 19 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesis
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موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
![عکس صفحه اول مقاله: Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesis Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesis](/preview/png/541461.png)
چکیده انگلیسی
This paper demonstrates the reversible fault tolerant logic synthesis for the Field Programmable Gate Array (FPGA) and its realization using MOS transistors. Algorithms to design a compact reversible fault tolerant n -to-2n2n decoder, 4n-to-n multiplexers, a random access memory and a Plessey logic block of the FPGA have been presented. In addition, several lower bounds on the numbers of garbage outputs, constant inputs and quantum cost of the FPGA have been proposed. The comparative results show that the proposed design is much better in terms of gate count, garbage outputs, quantum cost, delay, and hardware complexity than the existing approaches.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 44, Issue 6, June 2013, Pages 519–537
Journal: Microelectronics Journal - Volume 44, Issue 6, June 2013, Pages 519–537
نویسندگان
Md. Shamsujjoha, Hafiz Md. Hasan Babu, Lafifa Jamal,