Completion detection in dual-rail asynchronous systems by current-sensing

In this article, we address a novel methodology of detecting a computation completion of the combinatorial block in asynchronous digital systems. The proposed methodology is based on well-known phenomenon that occurs in digital systems realized in CMOS technology. CMOS logic circuits exhibit significantly higher current consumption during the signal transitions than in the static state. This effect can be exploited to separate the idle state from the computation process. The paper presents fundamental background of the completion detection methodology, detailed description of developed current sensor circuitry, achieved simulation results as well as the comparison with the state-of-the-art methods of completion detection and previous research that has been done in this scientific area.