Design and simulation of novel adder/subtractors on quantum-dot cellular automata: Radical departure from Boolean logic circuits

The quantum-dot cellular automata (QCA) technology is now considered as one of the perspective technologies for a nanocomputer creation. The physical properties of QCA make it expedient to use serial data transfer/processing. The use of decimal notation and decimal arithmetic in QCA computing eliminates the decimal-to-binary conversion errors and processor time loses for these conversions, and also simplifies the software and increases the computer reliability. The 5-bit decimal Johnson-Mobius encoding simplifies decimal processing algorithms and allows error detection. The paper presents two original serial decimal adder/subtractor designs and a simple change-of-level Johnson-Mobius code error detector design on QCA. The radical departure from traditional parallel Boolean logic processing allows the use of a delay element implemented by short length of QCA wire as a function element. Such approach results in QCA decimal hardware simplification.