Analysis and design of MOS current mode logic exclusive-OR gate using triple-tail cells

A new low-voltage MOS current mode logic (MCML) topology for an exclusive-OR (XOR) gate using triple-tail cell concept is proposed. The design of the proposed MCML XOR gate is carried out through analytical modeling of its static parameters. The delay is expressed in terms of the bias current and the voltage swing so that it can be traded off with the power consumption. The proposed low-voltage MCML XOR gate is analyzed for three design cases namely high-speed, power-efficient, and low-power and the performance is compared with the traditional MCML XOR gate for each design case. The theoretical propositions are validated through extensive SPICE simulations using TSMC 0.18 µm CMOS technology parameters.