کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
541587 | 871474 | 2014 | 8 صفحه PDF | دانلود رایگان |

This paper presents an area-efficient variable-length FFT algorithm for DVB-T2 receivers. A matrix-based approach is used to achieve a novel radix 28 algorithm that fulfils the DVB-T2 specifications. Several implementation techniques are proposed to apply in order to reduce the FFT core area, such as a variable datapath scaling approach, a memoryless CORDIC algorithm and an efficient FIFO implementation. The layout of the FFT processor is designed in XFAB 0.18μm CMOS technology. The proposed variable-length processor occupies a layout area of 6.75 mm2. Compared with the DVB-T2 designs in the literature, the proposed FFT processor presents the most area-efficient implementation. Furthermore, it provides a good power efficiency in the lower modes.
Journal: Microelectronics Journal - Volume 45, Issue 10, October 2014, Pages 1311–1318