FPGA based efficient on-chip memory for image processing algorithms

In Field Programmable Gate Array (FPGA) efficient utilization of on-chip Static Random Access Memory (SRAM) is extremely important for most applications especially for image processing. True Dual Port (TDP) SRAM and Single Port (SP) SRAM are typically available SRAMs for image processing algorithms. But in case of data access policy changes, the memories need to be redesigned. Hence on-chip memory architecture capable of scanning the data in different ways without redesigning is required. In the proposed sub-bank Dual Port (DP) memory architecture, SP SRAM has been modified to function as a TDP SRAM, with high throughput and less power consumption. It also provides higher level of abstraction suitable for image processing algorithms with the help of two-port memory control unit, clock and address generators. The proposed sub-bank memory architecture and its system is implemented and verified for Lapped Biorthogonal Transform based Low complexity Zerotree Codec (LBT-LZC), an image coding algorithm. By considering the significant factors such as resource utilization, time and power, the proposed system outperforms TDP SRAMs.