A low power voltage limiter for a full passive UHF RFID sensor on a 0.35 μm CMOS process

This paper presents a low power voltage limiter design for avoiding possible damages in the analog front-end of a RFID sensor due to voltage surges whenever readers and tags are close. The proposed voltage limiter design takes advantage of the implemented bandgap reference and voltage regulator blocks in order to provide low deviation of the limiting voltage due to temperature variation and process dispersion. The measured limiting voltage is 2.9 V with a voltage deviation of only ±0.065 V for the 12 measured dies. The measured current consumption is only 150 nA when the reader and the tag are far away, not limiting the sensitivity of the tag due to an undesired consumption in the voltage limiter. The circuit is implemented on a low cost 2P4M 0.35 μm CMOS technology.

► A RFID voltage limiter design with low power and low deviation of the limiting voltage.
► The measured limiting voltage is 2.9 V with a deviation of only ±0.065 V for the measured dies.
► The voltage limiter current consumption is only 150 nA when the reader and the tag are far away.
► Due to low current consumption, the voltage limiter does not limit the sensitivity of the tag.
► The voltage limiter is implemented on a low cost 2P4M 0.35 μm CMOS technology.