A 5-bit lumped 0.18-μm CMOS step attenuator with low insertion loss and low phase distortion in 3–22 GHz applications

A 5-bit lumped CMOS step attenuator with low insertion loss and low phase distortion is designed and simulated in this paper. The proposed attenuator is based on lumped switched bridged-T and π structure attenuators, and implemented with 0.18-μm CMOS technology. Different attenuation states are controlled by NMOS switches. The switches in series branches have channel-shunt resistance to minimize the on-resistance without increasing parasitic capacitance. The NMOS switches in shunt branches are body-floated to improve the power handling performance of the proposed attenuator. Each attenuation module has an inductive phase-compensate low-pass network. The attenuator is controlled with a 5-bit digital signal to achieve the maximum attenuation amplitude range of 0–31 dB with 1 dB increase at 3–22 GHz. The root mean square (RMS) amplitude errors for each one of the 32 states are less than 0.53 dB and the RMS insertion phase is less than 6.3° at 3–22 GHz. The insertion loss is 5.5–13 dB, and the input P1 dB is 18.4 dBm at 12.5 GHz.