کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
541813 871496 2011 9 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process
چکیده انگلیسی

This paper presents an 8×8 bit pipelined multiplier operating at 320 MHz under 0.5 V supply voltage. Using PMOS forward body bias technique, the modified full adder and the new D flip-flop with synchronous output are combined and implemented in the proposed pipelined multiplier to achieve high operation speed at supply voltages as low as 0.5 V. The proposed pipelined multiplier is fabricated in 130 nm CMOS process. It operates up to 320 MHz and the power consumption is only 1.48 mW at 0.5 V. Moreover, the power consumption of the proposed pipelined multiplier at 0.5 V is reduced over 5.7 times than that of the traditional architecture at 1.2 V. Thus, the proposed 8×8 bit pipelined multiplier is suitable for SoC and dynamic voltage frequency scaling applications.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 42, Issue 1, January 2011, Pages 43–51
نویسندگان
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