Floorplanning for low power IC design considering temperature variations

Non-uniformity in thermal profiles of integrated circuits (ICs) is an issue that threatens their performance and reliability. This paper investigates the correlation between the total power consumption and the temperature variations across a chip. As a result, floorplanning guidelines are proposed that uses the correlation to efficiently optimize the chip's total power and takes into account the thermal uniformity. It is demonstrated that optimizing a floorplan to minimize either the leakage or the peak temperature can lead to a significant increase in the total power consumption. In this paper, the experimental results show that lowering the temperature variations across a chip not only addresses performance degradation and reliability concerns, but also significantly contributes to chip power reduction. In addition, it is found that although uniformity in the thermal profile can be very effective in lowering the total power consumption, the most uniform temperature distribution does not necessarily correspond to the highest power savings. Consequently, for some applications, a 2% deviation from the minimum total power is traded for up to a 25% increase in thermal uniformity. The presented method is implemented for an Alpha 21264 processor running Spec 2000 benchmarks.