Detailed analysis of the effect of a hysteretic quantizer in a multibit, Sigma-Delta modulator

A detailed analysis of the impact of a hysteretic quantizer on a multibit, Sigma-Delta modulator has been carried out in this paper. Both discrete-time and continuous-time modulators have been considered. A qualitative modeling of the hysteretic quantizer based on a hysteretic block followed by an ideal quantizer was proposed. Due to the hysteresis effect, the quantizer output signal is delayed and distorted with respect to the quantizer input signal, where the delay causes a phase-shift independent on the signal frequency. Yet, the effect of the hysteresis depends on the input signal amplitude. This model was validated by using system-level simulations for a second order, 3-bit, discrete-time Sigma-Delta modulator. A linear model for hysteresis was derived by assuming a narrow hysteresis cycle. The quantizer input signal plays a fundamental role in the discussion. In order to include this signal into the linear analysis some approximations are proposed. The quantizer output signal is decomposed by the use of the Fourier series analysis only into the in-phase and quadrature components (with respect to the input signal) whose Fourier series coefficients can be analytically calculated. A quantitative analysis for both a second order, 3-bit, DT and CT Sigma-Delta modulators including a hysteretic quantizer was carried out. For the CT modulator, finite GBW in amplifiers, excess loop delay, and a hysteretic quantizer were considered separately and combined. A good agreement with both system-level simulations and experimental results is found, despite the approximations considered for the quantizer input signal.