Design investigation of nanoelectronic circuits using crossbar-based nanoarchitectures

Nanowire crossbar is an efficient nanoscale architecture which can be used for logic circuit design. In this work, we study and compare different crossbar nanoarchitectures and their application in logic circuit implementation. To evaluate the performance of crossbar architecture compared to the conventional CMOS logic design, we have implemented logic circuits using both approaches. The equivalent circuit models of the crossbar-based circuits are then extracted and simulated using HSPICE. The CMOS circuits are also simulated using 22-nm technology parameters. Our simulation results show that crossbar-based circuits have much smaller area while CMOS circuits show better performance in terms of delay. We implemented area optimized cell libraries based on the crossbar architecture which considerably reduces circuit area. Simulation results of benchmark circuits using SIS synthesis tool indicate that the crossbar cells can be combined with CMOS cells to achieve tradeoff between circuit area and speed.