An efficient architecture for accumulator-based test generation of SIC pairs

Research conducted over the years has shown that the application of single input change (SIC) pairs of test patterns for sequential, i.e. stuck-open and delay fault testing is extremely efficient. In this paper, a novel architecture for the generation of SIC pairs is presented. The implementation of the proposed architecture is based on Ling adders that are commonly utilized in current data paths due to their high-operating speed. Since the timing characteristics of the adder are not modified, the presented architecture provides a practical solution for the built-in testing of circuits that contain such adders.