کد مقاله | کد نشریه | سال انتشار | مقاله انگلیسی | نسخه تمام متن |
---|---|---|---|---|
541986 | 871510 | 2010 | 8 صفحه PDF | دانلود رایگان |
عنوان انگلیسی مقاله ISI
Variable-amplitude dither-based digital background calibration algorithm for linear and high-order nonlinear error in pipelined ADCs
دانلود مقاله + سفارش ترجمه
دانلود مقاله ISI انگلیسی
رایگان برای ایرانیان
کلمات کلیدی
موضوعات مرتبط
مهندسی و علوم پایه
مهندسی کامپیوتر
سخت افزارها و معماری
پیش نمایش صفحه اول مقاله

چکیده انگلیسی
Dither-based digital background calibration algorithm has been used to eliminate the influence of linear and nonlinear errors in pipelined ADC. However, this algorithm suffers from two disadvantages: too slow convergent speed and deduction of transmitting signal’s amplitude in analog circuits due to dither injection. Input-dependent variable-amplitude dither-based algorithm is used in this paper to conquer both disadvantages. This proposed algorithm is implemented in a 14-bit, 100 MHz sample-rate pipelined ADC. The simulation results illustrate signal-to-noise and distortion (SINAD) of 76.56 dB after calibration of linear and nonlinear errors. Furthermore, the convergent speed is improved much more.
ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 41, Issue 7, July 2010, Pages 403–410
Journal: Microelectronics Journal - Volume 41, Issue 7, July 2010, Pages 403–410
نویسندگان
Shuo Yang, Jun Cheng, Pei Wang,