An IEEE 1149.1-based BIST method for at-speed testing of inter-switch links in network on chip

With advance in technology and working frequency reaching gigahertz, designing and testing interconnects have become an important issue. In this paper, we proposed a BIST-based boundary scan architecture to at-speed test of crosstalk faults for inter-switch communication links in network on chip. This architecture includes enhanced cells intended for MVT model test patterns generation and analysis test responses. One new instruction is used to control cells and TPG controller in the at-speed test mode in order to fully comply with conventional IEEE 1149.1 standard.