A 15fJ/conversion-step 8-bit 50 MS/s asynchronous SAR ADC with efficient charge recycling technique

An 8-bit successive approximation analog-to-digital converter (ADC) with small area and high power efficiency is presented in this paper. The proposed ADC includes digital foreground calibrated comparator and a novel capacitor switching method. The former one uses programmable voltage coming from resistive divider to control the bulk of latch input differential pair, therefore comparison speed does not need to compromise and the nonlinearity introduced by variation of input capacitance is reduced. The latter one utilizes two separated capacitor arrays in a post-comparison and binary tree manner so as to save power consumption of charge recycling. Moreover, asynchronous timing control and reference-free architecture is implemented to further decrease the power and simplify auxiliary circuits for ADC. It is designed in a 65 nm digital CMOS process, achieving 49.9 dB signal-to-noise-and-distortion-ratio (SNDR) and 72.0 dB spurious-free-dynamic-range (SFDR) at the sampling rate of 50 MS/s while consuming 192.8 μW from 1 V power supply. The figure of merit is as low as 15fJ/conversion-step.