A linearized technique in an All-MOS transconductance amplifier

A linearized technique in an all-MOS transconductance amplifier is presented. This proposed technique utilizes a simple source follower without the need of complex circuits. The linearization principle and the design methodology are demonstrated in this paper. The corresponding circuit has been fabricated in a 0.35μm CMOS technology, and its active chip area is 145.8×79.6μm2. From the experimental results, the proposed technique improves the nonlinearity error from 10.92% to 0.64% at a 3.3 V supply voltage.