کد مقاله کد نشریه سال انتشار مقاله انگلیسی نسخه تمام متن
542067 871518 2011 6 صفحه PDF دانلود رایگان
عنوان انگلیسی مقاله ISI
High speed sample and hold design using closed-loop pole-zero cancelation
موضوعات مرتبط
مهندسی و علوم پایه مهندسی کامپیوتر سخت افزارها و معماری
پیش نمایش صفحه اول مقاله
High speed sample and hold design using closed-loop pole-zero cancelation
چکیده انگلیسی

A new closed loop Sample-and-Hold (S&H) architecture is proposed for pipeline analog-to-digital converter (ADC) that breaks the precision-speed-power trade off by means of canceling out the first closed loop pole. This pole-canceling results in widening the bandwidth of the S&H up to the second pole. In this architecture, two amplifiers are used: one for accuracy with little power consumption, another one for high-speed response, which consumes most of the total power. Exploiting these two amplifiers remedies some of the tradeoffs and limitations of opamp design in S&H circuits. Simulated by HSPICE with a standard BSIM3v3 0.13 μm technology, the S&H achieves 80 dB SFDR for a 1.6 Vppd output at 500 MHz sampling rate.

ناشر
Database: Elsevier - ScienceDirect (ساینس دایرکت)
Journal: Microelectronics Journal - Volume 42, Issue 12, December 2011, Pages 1353–1358
نویسندگان
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